培(pei)訓(xun)方式以講課和實驗(yan)穿(chuan)插進(jin)行(xing)。
課程描述：
Category:?Front End
Course Description
In the Allegro? FPGA System Planner (FSP) course, you learn to define your FPGA system and synthesize the connections in your design. You generate a schematic and PCB Editor database, so the FPGA I/O assignments can be optimized in the board environment.
Learning Objectives
After completing this course, you will be able to:
- Identify how data flows from the FPGA System Planner (FSP) to the schematic and PCB
- Create a design in FSP
- Define the protocols and interfaces in an FSP design
- Synthesize the connections in FSP protocols and interfaces
- Add terminations and external ports in an FSP design
- Generate an Allegro Design Entry HDL schematic from your FSP design
- Export your FSP placement to the PCB Editor
- Back annotate pin swaps and design changes from the schematic and PCB Editor to FSP
Software Used in This Course
- Allegro FPGA System Planner
- Allegro Design Entry HDL
Software Release(s)
Course Agenda
Note that this course can be tailored to better meet your needs?–?contact the Cadence training staff?for specifics.
Day 1
- FPGA System Creation
- FPGA System Synthesis
- FPGA System Completion
Day 2
- Integration with Design Entry HDL and PCB Editor
- Postlayout Optimization
- Importing FPGA Constraint Files and Virtual Interfaces
- FSP Models
Audience
- Design Engineers
- FPGA Designers
- PCB Designers
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